`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/11 15:56:48
// Design Name: 
// Module Name: TOP_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module TOP_tb(

    );
    
    reg[2:0] A_tb;
    reg[2:0] B_tb;
    reg APM, BPM;
    
    wire a,b,c,d,e,f,g;
    wire en3_tb, en2_tb, en1_tb, en0_tb;
    wire PMA_tb, PMB_tb, PMY_tb;
    
    integer ai,bi;
    initial
    begin
        for (ai = 0; ai < 8; ai = ai + 1)
        begin
            for (bi = 0; bi < 8; bi = bi + 1)
            begin
                A_tb = ai;
                B_tb = bi;
                #200; APM = 0; BPM = 0;
                #200; APM = 0; BPM = 1;
                #200; APM = 1; BPM = 0;
                #200; APM = 1; BPM = 1;
            end
        end
    end
    
    EDA1_TOP_v3_wrapper top_bd_wrapper(  
        .A0(A_tb[0]),
        .A1(A_tb[1]),
        .A2(A_tb[2]),
        .APM(APM),
        .B0(B_tb[0]),
        .B1(B_tb[1]),
        .B2(B_tb[2]),
        .BPM(BPM),
        .DA(a),
        .DB(b),
        .DC(c),
        .DD(d),
        .DE(e),
        .DF(f),
        .DG(g),
        .EN3(en3_tb),
        .EN2(en2_tb),
        .EN1(en1_tb),
        .EN0(en0_tb),
        .PMA(PMA_tb),
        .PMB(PMB_tb),
        .PMY(PMY_tb)
     );
endmodule
